Modeling Theorist
Seeking a theorist to model HgCdTe semiconductor material growth on silicon for improved infrared detectors, aiming to reduce defects and enhance performance.
This grant is no longer accepting proposals
NRC Research Associateship Programs has archived this opportunity.
Funder: NRC Research Associateship Programs
Due Dates: May 1, 2025 (RDEC/NVESD opportunity)
Funding Amounts: $75,000 base stipend plus $2,000 travel allowance; experience-based supplements available; typical postdoctoral fellowship duration 2-3 years.
Summary: Postdoctoral fellowship for a theorist to model HgCdTe semiconductor growth on silicon substrates to improve infrared detector performance by reducing defects and enhancing material quality.
Key Information: Open to U.S. citizens with a PhD earned within the last 5 years; research conducted at U.S. Army RDEC/NVESD in Fort Belvoir, VA; relocation and health insurance benefits included.
Description
This postdoctoral research opportunity focuses on advancing semiconductor materials for next-generation infrared detectors, specifically modeling the growth of HgCdTe (mercury cadmium telluride) on silicon substrates. HgCdTe is the preferred material for long-wave infrared (LWIR, 8-12 μm) and very long-wave infrared (VLWIR, 12-15 μm) detectors. Traditionally, HgCdTe epilayers are grown on lattice-matched CdZnTe substrates, which are costly, brittle, limited in size, and thermally mismatched with silicon readout circuitry.
Silicon substrates offer advantages such as lower cost, larger wafer sizes (improving production yield), compatibility with standard semiconductor processing, mechanical strength, and excellent thermal matching to silicon readout circuits. However, a significant 19% lattice mismatch between silicon and HgCdTe causes high dislocation densities (~1×10^7 cm^-2) in the epilayers, especially problematic for LWIR and VLWIR detectors, leading to reduced quantum efficiency and operability.
To address this, buffer layers of II-VI materials (starting with monolayer arsenic coverage on silicon, followed by thin ZnTe and ~10 μm CdTe layers) are used to improve crystallinity. Despite improvements, dislocation densities remain high, and the mechanisms behind defect formation and their impact on electrical performance require detailed investigation.
The fellow will use advanced material studio modeling and high-performance computing to simulate HgCdTe growth on silicon, aiming to understand defect generation due to lattice mismatch and to develop strategies to mitigate these defects. Experimental validation will be conducted at the Night Vision and Electronic Sensors Directorate (NVESD) using molecular beam epitaxy systems capable of producing the buffer layers and HgCdTe epilayers on silicon. Iterative cycles of modeling, growth, and characterization will refine understanding and improve material quality.
This research will advance solid-state physics modeling of HgCdTe and contribute to a collaborative team effort focused on improving infrared detector materials.
